EDN

“Do’s and Don’ts” when considering an FPGA to structured ASIC design methodology

More and more engineers are considering structured ASICs when they are designing advanced systems, because these components offer low unit cost, low power, and high performance along with fast ...
Design-Reuse

Domino Logic in ASIC Design Flow - Detailed Methodology and Breakthroughs in High Speed Design Automation Approach

Geneva -- September 22,2008 - Engineers at STMicroelectronic have revealed how to use domino logic, a very fast circuit design style utilized in the highest performance custom designs,in an automated ...
Design-Reuse

Open-Silicon Awarded Patent for Low Power ASIC Design Methodology

MILPITAS, Calif. – September 14, 2011 – Open-Silicon, Inc., a leading SoC design and semiconductor manufacturing company, announced today that the United States Patent and Trademark Office has ...
EDN

Hierarchical design methodology supports complex FPGAs

FPGA devices have grown to ASIC size and complexity, but traditional EDA tools and methodologies have failed to keep pace. Engineers designing high-end FPGAs are beginning to face the types of ...
Semiconductor Engineering

Achieving eFPGA Timing Closure In An ASIC

When we start school as young children, one of the first lessons we learn is how to share, followed quickly by not running with scissors. As Kent Orthner, Achronix’s senior director of Systems ...
manilatimes

Presto Engineering Group Acquires Garfield Microelectronics Ltd, Creating Europe’s Most Comprehensive ASIC Design to Production One-Stop-Shop

Custom hardware platform used for ASIC validation and test development MEYREUIL, France, Nov. 27, 2025 (GLOBE NEWSWIRE) -- Presto Engineering Group, a global leader in ASIC supply and semiconductor ...
Semiconductor Engineering

Shoot The Engineer

Many years ago as a junior engineer right out of college, my manager explain to me the concept of “shoot the engineer.” Engineers are trained to be perfectionists. We want to design the best mouse ...